1. Field of the Invention
The present invention relates to a circuit for detecting a negative word line voltage, and more particularly to a circuit for detecting a negative word line voltage which can detect levels of a plurality of negative word line voltages by using test signals without modifying the circuit.
2. Description of the Background Art
A DRAM applies about −0.3V of negative word line voltage VBBW lower than 0V to 3.0V of high voltage VPP to a word line in order to control the word line. Accordingly, the DRAM stably controls the word line by reducing a leakage current, thereby stabilizing the circuit.
FIG. 1 is a structure diagram illustrating a conventional circuit for detecting a negative word line voltage.
As illustrated in FIG. 1, a first PMOS transistor P11 driven according to a ground voltage VSS is diode-coupled between a power supply terminal VCORE and a first node Q11, and first to third NMOS transistors N11 to N13 are diode-coupled between the first node Q11 and a negative word line voltage terminal VBBW. Here, it is desirable to change −1V to +1V of negative word line voltage VBBW to obtain a wanted negative word line voltage VBBW. Therefore, a potential of the first node Q11 is changed according to the negative word line voltage VBBW, having a difference of threshold voltages of the first to third NMOS transistors N11 to N13. When the potential of the first node Q11 is greater than a threshold voltage of an NMOS transistor of an inverter I11, the NMOS transistor is turned on to output a signal having ground voltage level VSS, and the signal is inverted through a second inverter I12 as a high state signal. Here, the operator acquires the negative word line voltage VBBW.
However, referring to FIG. 2 showing simulation results of the circuit of FIG. 1, the conventional circuit detects only one voltage level. When a wanted voltage level is not obtained due to a temperature or other process factors, the circuit must be modified. In the case that the circuit is modified, the whole process and tests must be re-performed to obtain the modified circuit, which remarkably increases time and expenses. As a result, the development of the products is delayed and the forwarding time of the products is lost, to reduce competitiveness.